An Interprocedural Parallelizing Compiler and Its Support for Memory Hierarchy Research

We present several new compiler techniques employed by our interprocedural parallelizing research compiler, Panorama, to improve loop parallelization and the eeciency of memory references. We rst present an overview of the compiler and its associated memory architecture simulation environments. We then present an interprocedural array dataaow analysis, using guarded array regions, for automatic array privatization , an interprocedural static proole analysis, and a graph coloring scheme for parallel task assignment and data allocation which aims at reducing remote memory references while maintaining loop parallelism.